Class

Chisel

CompatibilityModule

Related Doc: package Chisel

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abstract class CompatibilityModule extends LegacyModule

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Inherited
  1. CompatibilityModule
  2. LegacyModule
  3. ImplicitModule
  4. UserModule
  5. BaseModule
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Instance Constructors

  1. new CompatibilityModule(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions)

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  2. new CompatibilityModule(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)

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  3. new CompatibilityModule(_clock: Clock)(implicit moduleCompileOptions: CompileOptions)

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  4. new CompatibilityModule(override_clock: Option[Clock] = None, override_reset: Option[Bool] = None)(implicit moduleCompileOptions: CompileOptions)

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Abstract Value Members

  1. abstract def io: chisel3.core.Record

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    Definition Classes
    LegacyModule

Concrete Value Members

  1. final def !=(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any
  2. final def ##(): Int

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    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean

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    Definition Classes
    AnyRef → Any
  4. def IO[T <: chisel3.core.Data](iodef: T): iodef.type

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    This must wrap the datatype used to set the io field of any Module.

    This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

    Items in [] are optional.

    The granted iodef WILL NOT be cloned (to allow for more seamless use of anonymous Bundles in the IO) and thus CANNOT have been bound to any logic. This will error if any node is bound (e.g. due to logic in a Bundle constructor, which is considered improper).

    Also registers a Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

    TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _autoWrapPorts(): Unit

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    Compatibility function.

    Compatibility function. Allows Chisel2 code which had ports without the IO wrapper to compile under Bindings checks. Does nothing in non-compatibility mode.

    Should NOT be used elsewhere. This API will NOT last.

    TODO: remove this, perhaps by removing Bindings checks in compatibility mode.

    Definition Classes
    CompatibilityModuleBaseModule
  6. var _closed: Boolean

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    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _ioPortBound(): Boolean

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    Attributes
    protected
    Definition Classes
    LegacyModule
  8. def annotate(annotation: ChiselAnnotation): Unit

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    Attributes
    protected
    Definition Classes
    BaseModule
  9. final def asInstanceOf[T0]: T0

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    Definition Classes
    Any
  10. val clock: chisel3.core.Clock

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    Definition Classes
    ImplicitModule
  11. def clone(): AnyRef

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  12. val compileOptions: CompileOptions

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    Definition Classes
    UserModule
  13. def desiredName: String

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    Desired name of this module.

    Desired name of this module. Override this to give this module a custom, perhaps parametric, name.

    Definition Classes
    BaseModule
  14. final def eq(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef
  15. def equals(that: Any): Boolean

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    Definition Classes
    HasId → AnyRef → Any
  16. def finalize(): Unit

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    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  17. final def getClass(): Class[_]

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    Definition Classes
    AnyRef → Any
  18. def getCommands: Seq[Command]

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    Attributes
    protected
    Definition Classes
    UserModule
  19. def getIds: Seq[HasId]

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    Attributes
    protected
    Definition Classes
    BaseModule
  20. def getModulePorts: Seq[chisel3.core.Data]

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    Attributes
    protected
    Definition Classes
    BaseModule
  21. lazy val getPorts: Seq[Port]

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    Definition Classes
    UserModule
  22. def hashCode(): Int

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    Definition Classes
    HasId → AnyRef → Any
  23. def instanceName: String

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    Signal name (for simulation).

    Signal name (for simulation).

    Definition Classes
    BaseModule → HasId → InstanceId
  24. final def isInstanceOf[T0]: Boolean

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    Definition Classes
    Any
  25. final val name: String

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    Legalized name of this module.

    Legalized name of this module.

    Definition Classes
    BaseModule
  26. def nameIds(rootClass: Class[_]): HashMap[HasId, String]

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    Called at the Module.apply(...) level after this Module has finished elaborating.

    Called at the Module.apply(...) level after this Module has finished elaborating. Returns a map of nodes -> names, for named nodes.

    Helper method.

    Attributes
    protected
    Definition Classes
    LegacyModuleBaseModule
  27. final def ne(arg0: AnyRef): Boolean

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    Definition Classes
    AnyRef
  28. final def notify(): Unit

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    Definition Classes
    AnyRef
  29. final def notifyAll(): Unit

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    Definition Classes
    AnyRef
  30. var override_clock: Option[chisel3.core.Clock]

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    Attributes
    protected
    Definition Classes
    LegacyModule
  31. var override_reset: Option[chisel3.core.Bool]

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    Attributes
    protected
    Definition Classes
    LegacyModule
  32. def parentModName: String

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    Definition Classes
    HasId → InstanceId
  33. def parentPathName: String

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    Definition Classes
    HasId → InstanceId
  34. def pathName: String

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    Definition Classes
    HasId → InstanceId
  35. def portsContains(elem: chisel3.core.Data): Boolean

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    Attributes
    protected
    Definition Classes
    BaseModule
  36. def portsSize: Int

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    Attributes
    protected
    Definition Classes
    BaseModule
  37. val reset: chisel3.core.Reset

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    Definition Classes
    ImplicitModule
  38. def suggestName(name: ⇒ String): CompatibilityModule.this.type

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    Definition Classes
    HasId
  39. final def synchronized[T0](arg0: ⇒ T0): T0

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    Definition Classes
    AnyRef
  40. def toString(): String

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    Definition Classes
    AnyRef → Any
  41. final def wait(): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  42. final def wait(arg0: Long, arg1: Int): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  43. final def wait(arg0: Long): Unit

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    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Inherited from LegacyModule

Inherited from ImplicitModule

Inherited from UserModule

Inherited from BaseModule

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

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