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chisel3

core

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package core

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Type Members

  1. sealed abstract class ActualDirection extends AnyRef

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    Resolved directions for both leaf and container nodes, only visible after a node is bound (since higher-level specifications like Input and Output can override directions).

  2. sealed abstract class Aggregate extends Data

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    An abstract class for data types that solely consist of (are an aggregate of) other Data objects.

  3. final class Analog extends Element

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    Data type for representing bidirectional bitvectors of a given width

    Data type for representing bidirectional bitvectors of a given width

    Analog support is limited to allowing wiring up of Verilog BlackBoxes with bidirectional (inout) pins. There is currently no support for reading or writing of Analog types within Chisel code.

    Given that Analog is bidirectional, it is illegal to assign a direction to any Analog type. It is legal to "flip" the direction (since Analog can be a member of aggregate types) which has no effect.

    Analog types are generally connected using the bidirectional attach mechanism, but also support limited bulkconnect <>. Analog types are only allowed to be bulk connected *once* in a given module. This is to prevent any surprising consequences of last connect semantics.

    Note

    This API is experimental and subject to change

  4. abstract class BaseBlackBox extends BaseModule

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  5. abstract class BaseModule extends HasId

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    Abstract base class for Modules, an instantiable organizational unit for RTL.

  6. case class Binary(bits: Bits) extends FirrtlFormat with Product with Serializable

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    Format bits as Binary

  7. sealed trait Binding extends AnyRef

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  8. sealed abstract class BindingDirection extends AnyRef

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  9. sealed abstract class Bits extends Element with ToBoolable

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    A data type for values represented by a single bitvector.

    A data type for values represented by a single bitvector. Provides basic bitwise operations.

  10. abstract class BlackBox extends BaseBlackBox

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    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog.

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

    Example:
    1. Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:

      IBUFDS #(.DIFF_TERM("TRUE"),
               .IOSTANDARD("DEFAULT")) ibufds (
       .IB(ibufds_IB),
       .I(ibufds_I),
       .O(ibufds_O)
      );

      To instantiate it, a BlackBox can be used like following:

      import chisel3._
      import chisel3.experimental._
      // Example with Xilinx differential buffer IBUFDS
      class IBUFDS extends BlackBox(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
                                        "IOSTANDARD" -> "DEFAULT"
                           )) {
        val io = IO(new Bundle {
          val O = Output(Clock()) // IO names will be the same
          val I = Input(Clock())  // (without 'io_' in prefix)
          val IB = Input(Clock()) //
        })
      }
    Note

    The parameters API is experimental and may change

  11. sealed class Bool extends UInt with Reset

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    A data type for booleans, defined as a single bit indicating true or false.

  12. trait BoolFactory extends AnyRef

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  13. class Bundle extends Record

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    Base class for data types defined as a bundle of other data types.

    Base class for data types defined as a bundle of other data types.

    Usage: extend this class (either as an anonymous or named class) and define members variables of Data subtypes to be elements in the Bundle.

    Example of an anonymous IO bundle

    class MyModule extends Module {
      val io = IO(new Bundle {
        val in = Input(UInt(64.W))
        val out = Output(SInt(128.W))
      })
    }

    Or as a named class

    class Packet extends Bundle {
      val header = UInt(16.W)
      val addr   = UInt(16.W)
      val data   = UInt(32.W)
    }
    class MyModule extends Module {
       val io = IO(new Bundle {
         val inPacket = Input(new Packet)
         val outPacket = Output(new Packet)
       })
       val reg = Reg(new Packet)
       reg <> inPacket
       outPacket <> reg
    }
  14. case class Character(bits: Bits) extends FirrtlFormat with Product with Serializable

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    Format bits as Character

  15. case class ChildBinding(parent: Data) extends Binding with Product with Serializable

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  16. case class ChiselAnnotation(component: InstanceId, transformClass: Class[_ <: Transform], value: String) extends Product with Serializable

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    This is a stand-in for the firrtl.Annotations.Annotation because at the time this annotation is created the component cannot be resolved, into a targetString.

    This is a stand-in for the firrtl.Annotations.Annotation because at the time this annotation is created the component cannot be resolved, into a targetString. Resolution can only happen after the circuit is elaborated

    component

    A chisel thingy to be annotated, could be module, wire, reg, etc.

    transformClass

    A fully-qualified class name of the transformation pass

    value

    A string value to be used by the transformation pass

  17. sealed class Clock extends Element

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  18. trait CompileOptions extends AnyRef

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  19. sealed trait ConstrainedBinding extends TopBinding

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  20. abstract class Data extends HasId

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    This forms the root of the type system for wire data types.

    This forms the root of the type system for wire data types. The data value must be representable as some number (need not be known at Chisel compile time) of bits, and must have methods to pack / unpack structured data to / from bits.

  21. case class Decimal(bits: Bits) extends FirrtlFormat with Product with Serializable

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    Format bits as Decimal

  22. case class DoubleParam(value: Double) extends Param with Product with Serializable

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  23. abstract class Element extends Data

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    Element is a leaf data type: it cannot contain other Data objects.

    Element is a leaf data type: it cannot contain other Data objects. Example uses are for representing primitive data types, like integers and bits.

  24. abstract class ExtModule extends BaseBlackBox

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    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog.

    Defines a black box, which is a module that can be referenced from within Chisel, but is not defined in the emitted Verilog. Useful for connecting to RTL modules defined outside Chisel.

    A variant of BlackBox, this has a more consistent naming scheme in allowing multiple top-level IO and does not drop the top prefix.

    Example:
    1. Some design require a differential input clock to clock the all design. With the xilinx FPGA for example, a Verilog template named IBUFDS must be integrated to use differential input:

      IBUFDS #(.DIFF_TERM("TRUE"),
               .IOSTANDARD("DEFAULT")) ibufds (
       .IB(ibufds_IB),
       .I(ibufds_I),
       .O(ibufds_O)
      );

      To instantiate it, a BlackBox can be used like following:

      import chisel3._
      import chisel3.experimental._
      // Example with Xilinx differential buffer IBUFDS
      class IBUFDS extends ExtModule(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
                                         "IOSTANDARD" -> "DEFAULT"
                           )) {
        val O = IO(Output(Clock()))
        val I = IO(Input(Clock()))
        val IB = IO(Input(Clock()))
      }
    Note

    The parameters API is experimental and may change

  25. sealed abstract class FirrtlFormat extends Printable

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    Superclass for Firrtl format specifiers for Bits

  26. sealed class FixedPoint extends Bits with Num[FixedPoint]

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    A sealed class representing a fixed point number that has a bit width and a binary point The width and binary point may be inferred.

    A sealed class representing a fixed point number that has a bit width and a binary point The width and binary point may be inferred.

    IMPORTANT: The API provided here is experimental and may change in the future.

  27. case class FullName(data: Data) extends Printable with Product with Serializable

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    Put full name within parent namespace (eg.

    Put full name within parent namespace (eg. bundleName.field)

  28. case class Hexadecimal(bits: Bits) extends FirrtlFormat with Product with Serializable

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    Format bits as Hexidecimal

  29. abstract class ImplicitModule extends UserModule

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    Abstract base class for Modules, which behave much like Verilog modules.

    Abstract base class for Modules, which behave much like Verilog modules. These may contain both logic and state which are written in the Module body (constructor).

    Note

    Module instantiations must be wrapped in a Module() call.

  30. case class IntParam(value: BigInt) extends Param with Product with Serializable

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  31. abstract class LegacyModule extends ImplicitModule

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    Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor for threading through explicit clock and reset.

    Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor for threading through explicit clock and reset.

    While this class isn't planned to be removed anytime soon (there are benefits to restricting IO), the clock and reset constructors will be phased out. Recommendation is to wrap the module in a withClock/withReset/withClockAndReset block, or directly hook up clock or reset IO pins.

  32. case class LitBinding() extends UnconstrainedBinding with Product with Serializable

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  33. sealed class Mem[T <: Data] extends MemBase[T]

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    A combinational/asynchronous-read, sequential/synchronous-write memory.

    A combinational/asynchronous-read, sequential/synchronous-write memory.

    Writes take effect on the rising clock edge after the request. Reads are combinational (requests will return data on the same cycle). Read-after-write hazards are not an issue.

    Note

    when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)

  34. sealed abstract class MemBase[T <: Data] extends HasId

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  35. case class MemoryPortBinding(enclosure: UserModule) extends ConstrainedBinding with Product with Serializable

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  36. case class Name(data: Data) extends Printable with Product with Serializable

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    Put innermost name (eg.

    Put innermost name (eg. field of bundle)

  37. trait Num[T <: Data] extends AnyRef

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    Abstract trait defining operations available on numeric-like wire data types.

  38. case class OpBinding(enclosure: UserModule) extends ConstrainedBinding with Product with Serializable

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  39. case class PString(str: String) extends Printable with Product with Serializable

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    Wrapper for printing Scala Strings

  40. sealed abstract class Param extends AnyRef

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    Parameters for BlackBoxes

  41. case class PortBinding(enclosure: BaseModule) extends ConstrainedBinding with Product with Serializable

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  42. sealed abstract class Printable extends AnyRef

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    Superclass of things that can be printed in the resulting circuit

    Superclass of things that can be printed in the resulting circuit

    Usually created using the custom string interpolator p"..." TODO Add support for names of Modules Currently impossible because unpack is called before the name is selected Could be implemented by adding a new format specifier to Firrtl (eg. %m) TODO Should we provide more functions like map and mkPrintable?

  43. case class Printables(pables: Iterable[Printable]) extends Printable with Product with Serializable

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  44. sealed trait PrivateType extends AnyRef

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    Use PrivateObject to force users to specify width and binaryPoint by name

  45. case class RawParam(value: String) extends Param with Product with Serializable

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    Unquoted String

  46. abstract class Record extends Aggregate

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    Base class for Aggregates based on key values pairs of String and Data

    Base class for Aggregates based on key values pairs of String and Data

    Record should only be extended by libraries and fairly sophisticated generators. RTL writers should use Bundle. See Record#elements for an example.

  47. case class RegBinding(enclosure: UserModule) extends ConstrainedBinding with Product with Serializable

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  48. sealed trait Reset extends Element with ToBoolable

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  49. sealed class SInt extends Bits with Num[SInt]

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  50. trait SIntFactory extends AnyRef

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  51. sealed abstract class SpecifiedDirection extends AnyRef

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    User-specified directions.

  52. case class StringParam(value: String) extends Param with Product with Serializable

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  53. sealed class SyncReadMem[T <: Data] extends MemBase[T]

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    A sequential/synchronous-read, sequential/synchronous-write memory.

    A sequential/synchronous-read, sequential/synchronous-write memory.

    Writes take effect on the rising clock edge after the request. Reads return data on the rising edge after the request. Read-after-write behavior (when a read and write to the same address are requested on the same cycle) is undefined.

    Note

    when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)

  54. sealed trait TopBinding extends Binding

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  55. sealed class UInt extends Bits with Num[UInt]

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    A data type for unsigned integers, represented as a binary bitvector.

    A data type for unsigned integers, represented as a binary bitvector. Defines arithmetic operations between other integer types.

  56. trait UIntFactory extends AnyRef

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  57. sealed trait UnconstrainedBinding extends TopBinding

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  58. abstract class UserModule extends BaseModule

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    Abstract base class for Modules that contain Chisel RTL.

  59. sealed class Vec[T <: Data] extends Aggregate with VecLike[T]

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    A vector (array) of Data elements.

    A vector (array) of Data elements. Provides hardware versions of various collection transformation functions found in software array implementations.

    Careful consideration should be given over the use of Vec vs Seq or some other scala collection. In general Vec only needs to be used when there is a need to express the hardware collection in a Reg or IO Bundle or when access to elements of the array is indexed via a hardware signal.

    Example of indexing into a Vec using a hardware address and where the Vec is defined in an IO Bundle

    val io = IO(new Bundle {
      val in = Input(Vec(20, UInt(16.W)))
      val addr = UInt(5.W)
      val out = Output(UInt(16.W))
    })
    io.out := io.in(io.addr)
    T

    type of elements

    Note

    • when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
    • Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier
  60. trait VecFactory extends AnyRef

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  61. trait VecLike[T <: Data] extends IndexedSeq[T] with HasId

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    A trait for Vecs containing common hardware generators for collection operations.

  62. final class WhenContext extends AnyRef

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    A WhenContext may represent a when, and elsewhen, or an otherwise.

    A WhenContext may represent a when, and elsewhen, or an otherwise. Since FIRRTL does not have an "elsif" statement, alternatives must be mapped to nested if-else statements inside the alternatives of the preceeding condition. In order to emit proper FIRRTL, it is necessary to keep track of the depth of nesting of the FIRRTL whens. Due to the "thin frontend" nature of Chisel3, it is not possible to know if a when or elsewhen has a succeeding elsewhen or otherwise; therefore, this information is added by preprocessing the command queue.

  63. case class WireBinding(enclosure: UserModule) extends ConstrainedBinding with Product with Serializable

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  64. trait WireFactory extends AnyRef

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  65. implicit class fromBigIntToLiteral extends AnyRef

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    These implicit classes allow one to convert scala.Int|scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.

    These implicit classes allow one to convert scala.Int|scala.BigInt to Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively. The versions .asUInt(width)|.asSInt(width) are also available to explicitly mark a width for the new literal.

    Also provides .asBool to scala.Boolean and .asUInt to String

    Note that, for stylistic reasons, one should avoid extracting immediately after this call using apply, ie. 0.asUInt(1)(0) due to potential for confusion (the 1 is a bit length and the 0 is a bit extraction position). Prefer storing the result and then extracting from it.

    Implementation note: the empty parameter list (like U()) is necessary to prevent interpreting calls that have a non-Width parameter as a chained apply, otherwise things like 0.asUInt(16) (instead of 16.W) compile without error and produce undesired results.

  66. implicit class fromBooleanToLiteral extends AnyRef

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  67. implicit class fromDoubleToLiteral extends AnyRef

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  68. implicit class fromIntToBinaryPoint extends AnyRef

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  69. implicit class fromIntToLiteral extends fromBigIntToLiteral

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  70. implicit class fromIntToWidth extends AnyRef

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  71. implicit class fromLongToLiteral extends fromBigIntToLiteral

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  72. implicit class fromStringToLiteral extends AnyRef

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Value Members

  1. object ActualDirection

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  2. object Analog

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    Object that provides factory methods for Analog objects

    Object that provides factory methods for Analog objects

    Note

    This API is experimental and subject to change

  3. object BiConnect

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    BiConnect.connect executes a bidirectional connection element-wise.

    BiConnect.connect executes a bidirectional connection element-wise.

    Note that the arguments are left and right (not source and sink) so the intent is for the operation to be commutative.

    The connect operation will recurse down the left Data (with the right Data). An exception will be thrown if a movement through the left cannot be matched in the right (or if the right side has extra fields).

    See elemConnect for details on how the root connections are issued.

  4. object Binding

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  5. object BindingDirection

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  6. object Bits extends UIntFactory

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  7. object Bool extends BoolFactory

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  8. object Clock

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  9. object CompileOptions

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  10. object DataMirror

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    Experimental hardware construction reflection API

  11. object ExplicitCompileOptions

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  12. object FirrtlFormat

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  13. object FixedPoint

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    Factory and convenience methods for the FixedPoint class IMPORTANT: The API provided here is experimental and may change in the future.

  14. object Flipped

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  15. object Input

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    Input, Output, and Flipped are used to define the directions of Module IOs.

    Input, Output, and Flipped are used to define the directions of Module IOs.

    Note that they currently clone their source argument, including its bindings.

    Thus, an error will be thrown if these are used on bound Data

  16. object Mem

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  17. object Module

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  18. object MonoConnect

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    MonoConnect.connect executes a mono-directional connection element-wise.

    MonoConnect.connect executes a mono-directional connection element-wise.

    Note that this isn't commutative. There is an explicit source and sink already determined before this function is called.

    The connect operation will recurse down the left Data (with the right Data). An exception will be thrown if a movement through the left cannot be matched in the right. The right side is allowed to have extra Record fields. Vecs must still be exactly the same size.

    See elemConnect for details on how the root connections are issued.

    Note that a valid sink must be writable so, one of these must hold: - Is an internal writable node (Reg or Wire) - Is an output of the current module - Is an input of a submodule of the current module

    Note that a valid source must be readable so, one of these must hold: - Is an internal readable node (Reg, Wire, Op) - Is a literal - Is a port of the current module or submodule of the current module

  19. object Mux

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  20. object Output

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  21. object Percent extends Printable with Product with Serializable

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    Represents escaped percents

  22. object Printable

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  23. object Reg

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  24. object RegInit

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  25. object RegNext

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  26. object SInt extends SIntFactory

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  27. object SpecifiedDirection

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  28. object SyncReadMem

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  29. object UInt extends UIntFactory

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  30. object Vec extends VecFactory

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  31. object VecInit

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  32. object Wire extends WireFactory

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  33. object WireInit

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  34. object assert

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  35. object attach

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  36. object dontTouch

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    Marks that a signal should not be removed by Chisel and Firrtl optimization passes

    Marks that a signal should not be removed by Chisel and Firrtl optimization passes

    Example:
    1. class MyModule extends Module {
        val io = IO(new Bundle {
          val a = Input(UInt(32.W))
          val b = Output(UInt(32.W))
        })
        io.b := io.a
        val dead = io.a +% 1.U // normally dead would be pruned by DCE
        dontTouch(dead) // Marking it as such will preserve it
      }
    Note

    Calling this on Data creates an annotation that Chisel emits to a separate annotations file. This file must be passed to Firrtl independently of the .fir file. chisel3.Driver.execute will do this automatically.

  37. object printf

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  38. object requireIsChiselType

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    Requires that a node is a chisel type (not hardware, "unbound")

  39. object requireIsHardware

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    Requires that a node is hardware ("bound")

  40. object stop

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  41. object when

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  42. object withClock

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  43. object withClockAndReset

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  44. object withReset

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Deprecated Value Members

  1. object debug

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    Annotations
    @deprecated
    Deprecated

    (Since version chisel3) debug doesn't do anything in Chisel3 as no pruning happens in the frontend

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