Object/Class

chisel3.util

Pipe

Related Docs: class Pipe | package util

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object Pipe

A hardware module that delays data coming down the pipeline by the number of cycles set by the latency parameter. Functionality is similar to ShiftRegister but this exposes a Pipe interface.

Example usage: val pipe = new Pipe(UInt()) pipe.io.enq <> produce.io.out consumer.io.in <> pipe.io.deq

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  1. final def !=(arg0: Any): Boolean

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  2. final def ##(): Int

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  3. final def ==(arg0: Any): Boolean

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  4. def apply[T <: Data](enq: Valid[T], latency: Int = 1)(implicit compileOptions: CompileOptions): Valid[T]

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  5. def apply[T <: Data](enqValid: Bool, enqBits: T)(implicit compileOptions: CompileOptions): Valid[T]

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  6. def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int)(implicit compileOptions: CompileOptions): Valid[T]

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  7. final def asInstanceOf[T0]: T0

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  8. def clone(): AnyRef

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  12. final def getClass(): Class[_]

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  14. final def isInstanceOf[T0]: Boolean

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  16. final def notify(): Unit

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  18. final def synchronized[T0](arg0: ⇒ T0): T0

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  22. final def wait(arg0: Long): Unit

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