This must wrap the datatype used to set the io field of any Module. i.e. All concrete modules must have defined io in this form: [lazy] val io[: io type] = IO(...[: io type])

Items in [] are optional.

The granted iodef must be a chisel type and not be bound to hardware.

Also registers an Data as a port, also performing bindings. Cannot be called once ports are requested (so that all calls to ports will return the same information). Internal API.

TODO(twigg): Specifically walk the Data definition to call out which nodes are problematic.

Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.

Hook to invoke hardware generators after the rest of the Module is constructed.

This is a power-user API, and should not normally be needed.

In rare cases, it is necessary to run hardware generators at a late stage, but still within the scope of the Module. In these situations, atModuleBodyEnd may be used to register such generators. For example:

class Example extends RawModule {
  atModuleBodyEnd {
    val extraPort0 = IO(Output(Bool()))
    extraPort0 := 0.B
  }
}

Any generators registered with atModuleBodyEnd are the last code to execute when the Module is constructed. The execution order is:

• The constructors of any super classes or traits the Module extends
• The constructor of the Module itself
• The atModuleBodyEnd generators

The atModuleBodyEnd generators execute in the lexical order they appear in the Module constructor.

For example:

trait Parent {
  // Executes first.
  val foo = ...
}

class Example extends Parent {
  // Executes second.
  val bar = ...

  atModuleBodyEnd {
    // Executes fourth.
    val qux = ...
  }

  atModuleBodyEnd {
    // Executes fifth.
    val quux = ...
  }

  // Executes third..
  val baz = ...
}

If atModuleBodyEnd is used in a Definition, any generated hardware will be included in the Definition. However, it is currently not possible to annotate any val within atModuleBodyEnd as @public.

Represents an eagerly-determined unique and descriptive identifier for this module

A non-ambiguous name of this Pipe for use in generated Verilog names. Includes the latency cycle count in the name as well as the parameterized generator's typeName, e.g. Pipe4_UInt4

Disallow any more IO creation for this module.

Method that should point to the user-defined Clock

Method that should point to the user-defined Reset

Signal name (for simulation).

Legalized name of this module.

Override this to explicitly set the type of reset you want on this module , before any reset inference

Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

Is a higher priority than autoSeed, in that regardless of whether autoSeed was called, suggestName will always take precedence.

Returns a FIRRTL ModuleTarget that references this object

Returns a FIRRTL ModuleName that references this object

Returns a FIRRTL ModuleTarget that references this object, relative to an optional root.

If root is defined, the target is a hierarchical path starting from root.

If root is not defined, the target is a hierarchical path equivalent to toAbsoluteTarget.

Returns a FIRRTL ModuleTarget that references this object