We would like to announce the preliminary SNAPSHOT release of Chisel3. Chisel3 is the Chisel version used by the RISC-V Rocket Chip Generator and is what we will be supporting and developing moving forward. As such, we highly encourage you all to move over to it. In order to do so, please import chisel3._ instead of Chisel._ in your Chisel designs. See migration from Chisel2 to Chisel3 for additional guidance.
We have been working very hard and long on Chisel3 and have moved over a large number of Chisel2 designs and have improved the interface to Chisel but have worked hard to maintain as much compatibility with Chisel2 as possible. In the future, we reserve the right to improve the visible Chisel3 API, but we will do so using a deprecation schedule and compatibility libraries.
Chisel3 is a significant upgrade from the 2.x releases of Chisel (Chisel2). Chisel3 generates FIRRTL – an intermediate representation (IR) for digital circuits, which is then translated by the FIRRTL compiler into Verilog.
We have switched from our C++ simulator to using Verilator. Verilator offers the advantages of having industry support and permitting cosimulation of Chisel and existing verilog. Given that it is based on translation of Verilog to C++ it will still allow you to write your own C++ code.
If you are new to Chisel, we suggest you start with the Chisel tutorial. This has been updated to reflect the new structure of Chisel3.
Documentation for Chisel3 can be found at the wikis associated with the GitHub code repos:
tutorial – basic introduction to Chisel
chisel3 – chisel3 core and utilities
template – a basic Chisel circuit suitable as a starting point for your design
testers – testing your design
firrtl – developer documentation
Jonathan Bachrach, Jim Lawson, and the rest of the Chisel Team