Does Chisel convert Scala to Verilog?

No Chisel is a hardware construction language for writing Scala programs that generate hardware

What's the overhead for Chisel?

None. Chisel allows designers to write circuits structurally as they do in Verilog with no extra overhead.

Why do I need SBT to compile and execute my Chisel code?

Technically you don't.

SBT is a builder for scala which is a cross between apt-get and make. It downloads all the prerequisites (as apt-get would do) then builds your chisel code (as make would do). The downloaded files will be cached in ~/.sbt and ~/.ivy2.

Chisel is packaged as a regular JAR file published on the sonatype repo. If you have your own build system, the bare minimum you need is to download the latest chisel jar file and execute the following commands (based on the example in the README file).

# Compile and execute your Chisel code
$ scalac-2.10 -cp chisel_2.10-2.2.27.jar Hello.scala
$ scala-2.10 -cp chisel_2.10-2.2.27.jar:. hello

# Compile and run the generated simulation
$ g++ -std=c++11 -o HelloModule HelloModule.cpp HelloModule-emulator.cpp
$ ./HelloModule 1

How can I make a vector of modules?

  Vec(Seq.fill(10)(Module(new CPU()))

How do I get in touch with the Chisel community?

There is a Chisel users Google group. You can also search for Chisel on Stack Overflow. To report bugs on the Chisel code itself, please open an issue on github.

How stable is Chisel?

Every night, we build all of Chisel and the projects listed in download with the help of a jenkins buildbot. Follow the unit tests trends here.

How did you get to work on such a cool project?

Chisel has been partially funded by

Thank you for your support!