Chisel 2.2.x

ReleaseNotes for Chisel v2.2.38 2017-04-24

This release of Chisel is a maintenance release, incorporating support for Chisel3's {as,to}{U,S}Int methods in all Chisel Data types.

We will be removing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.38 2017-04-24

Move {as,to}{U,S}Int definitions to Node.scala, and add them as Bundle key words.
Update deprecated Fill() usage in FillApp.scala.

ReleaseNotes for Chisel v2.2.37 2017-02-23

This release of Chisel is a maintenance release, incorporating a bug fix for issue #740 - unable to create a ROM with datawidth more than 64 bits.

We will be removing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.37 2017-02-23

#740 Wide rom fix
Remove Getting Started and refer to Chisel3.
Update README.md (point to Chisel3, add Resolvers to getting started build.sbt

ReleaseNotes for Chisel v2.2.36 2016-10-03

This release of Chisel is largely a maintenance release, incorporating some Chisel3 features and additional compatibility checks.

See the associated Changelog for issues resolved with this release.

We will be removing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.36 2016-10-03

Print Chisel version when Driver object is created.
Generate 'buildinfo' when Chisel jar is built.
Update sbt project name from "chisel" to "Chisel" (to match package name).
Add support for chisel3 wrappers (IO(), Input(), Output()).
Warn about uninstantiable backends.
Add scalacheck as a library dependency.
Move ChiselSpec.scala from test to main (required for new tester support).
Add Chisel3 clock methods.
Deprecate Fill(Chisel.Data, Int) and generate error in compatibility mode.

ReleaseNotes for Chisel v2.2.35 2016-07-22

This release of Chisel addresses a single issue, #718 - broken Vec fill.

We will be removing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.35 2016-07-22

#718 Remove extraneous apply() from vec.tabulate - Vec.fill appears to be badly broken

ReleaseNotes for Chisel v2.2.34 2016-07-01

This release of Chisel is largely a maintenance release, incorporating some Chisel3 features and additional compatibility checks.

See the associated Changelog for issues resolved with this release.

We will be removing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.34 2016-07-01

#710 Chisel3 compatibility: Allow asserts with empty messages
Rename testers to match chisel3.
Add chisel3 compatiblity stop()
MuxLookup should take Data, not just Bits
Add check for SInt <-> UInt connections.
Return Seq, not Vec, from PriorityEncoderOH
Use Seq, not Iterable, when order matters
Chisel3 compatibility: asUInt/asSInt must accept ()
Update to current sbt resolver idiom.
Added additional Chisel3 incompatibilities.
Compatibility check fixes
add package object with new literal creation implicits
Use the "real" cloneType mechanism to determine Chisel3 compatibility
Deal with empty Vec's when checking for element cloneType()
Revert to a single error list containing errors, checks, and warnings.
Convert exceptions into ChiselErrors so we don't give up on the first.
Migrated black box to separate file
Correct signature for vcd dump methods (lacked t and reset arguments).
Add SystemVerilog keywords to reserved word list
add /cpp directory to .gitignore
Improve log2* functions, as with Chisel3
Replace != with =/=

ReleaseNotes for Chisel v2.2.33 2016-04-14

This release of Chisel is largely a maintenance release. See the associated Changelog for issues resolved with this release.

We will be removing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.33 2016-04-14

#678,#180 [Tester] shut down processes when exceptions occur
#677 Changed index literals to base 10. for example, somewire[2'h3:1'h0] to somewire[3:0]
#675 [emulator] dump printfs between clock_lo & hi
#665,#692 Don't initialize the channels until we know how big they need to be.
#658 Issue informative error messages if errors at startup.
#655 Add Option types for Bundle.
Move documentation to a separate repo https://github.com/ucb-bar/chisel-doc
Fix memory access masking bug for nonPow2 memories
Bump sbt to version 0.13.11
Do not extract a single bit wire
Ensure reg_status is initialized.
Don't try Verilog tests if we don't have vcs available.
Make the package structure of hwiotesters in chisel2 emulate the two repo model used in chisel3
Add expect(Bool, Boolean) methods
Fix problem where isTrace is ignored for Flo & Dbl
Support wire_poke for Flo & Dbl.
Generate code compatible with the 1.7 JVM (cherry-pick from release).
Make vcd/vpd dump file configurable

ReleaseNotes for Chisel v2.2.32 2016-02-10

This release of Chisel includes support for Chisel3-style testers - testers as hardware. Currently, two basic hardware tester classes have been implemented: SteppedHWIOTester and OrderedDecoupledHWIOTester.

Use a SteppedHWIOTester to construct a direct (non-decoupled) test harness for a Chisel module. The module to be tested will be canonically referred to as the device_under_test (DUT), often simply as c in a specific test. This tester uses poke()'s to construct Vec's of values to be connected (in sequence) to the INPUT ports of the DUT. Similarly, expect()'s are used to construct Vec's of values expected to match the OUTPUT ports of the DUT.

For example, here is a simple adder and a SteppedHWIOTester class to test it.

class Adder(width:Int) extends Module {
  val io = new Bundle {
    val in0 = UInt(INPUT, width=width)
    val in1 = UInt(INPUT, width=width)
    val out = UInt(OUTPUT, width=width)
  }
  io.out := io.in0 + io.in1
}

class AdderTester extends SteppedHWIOTester {
  val device_under_test = Module( new Adder(32) )
  val c = device_under_test

  poke(c.io.in0, 5)
  poke(c.io.in1, 7)
  expect(c.io.out, 12)
}
implicit val args = Array[String]("--backend", "c", "--compile", "--genHarness", "--test")
TesterDriver.execute { () = >  new AdderTester }

The SteppedHWIOTester implements most of the functionality of the old Tester, using constructed hardware modules to do do. The missing piece is peek().

An OrderedDecoupledHWIOTester supports the implementation of test circuits of modules that use Decoupled input and either Decoupled or Valid output interfaces. Inputs to the DUT will flow into their devices asynchronously but in the order they were generated and outputs will be produced asynchronously and will be compared in the order they are generated. Inputs are specified by input events. An input event is a series of values that will be gated into the decoupled input interface at the same time. Outputs are specified by output events. An output event is a series of values that will be tested at the same time.

class XTimesYInput(width:Int) extends Bundle {
  val x = Bits(width = 16)
  val y = Bits(width = 16)
  override def cloneType = new XTimesYInput(width).asInstanceOf[this.type]
}

class XTimesY(width:Int) extends Module {
  val io = new Bundle {
    val in  = Decoupled(new XTimesYInput(width)).flip()
    val out = Decoupled(UInt(width = width))
  }
  io.out.bits := io.in.bits.x * io.in.bits.y
}

class XTimesXTester extends OrderedDecoupledHWIOTester {
  val device_under_test = Module( new XTimesY(16) )

  for {
    i  < - 0 to 10
    j  < - 0 to 10
  } {
    inputEvent(device_under_test.io.in.bits.x - >  i, device_under_test.io.in.bits.y - >  j)
    outputEvent(device_under_test.io.out.bits - >  i*j)
  }
}
implicit val args = Array[String]("--backend", "c", "--compile", "--genHarness", "--test")
TesterDriver.execute { () = >  new XTimesXTester }

Other examples of these hardware IO testers can be found in DecoupledGCD.scala and GCDUnitTest.scala in src/test/scala.

This area is in the early development stage, so expect some potentially significant changes before the API is stabilized.

A significant number of Scala style issues have been corrected, resulting in changes (whitespace only) to almost every source file. We are stricter with the enforcement of Scala style in Chisel3. This is an appetizer.

See the associated Changelog for additional issues resolved with this release.

We will be removing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.32 2016-02-10

#627 Dump vcd in module->clock()
#624 Try to avoid IndexOutOfBoundsException at the start of simulation.
#623 Print warning and return random for peeks of uwritten signales.
#621 Use low-level Extract instead of implementing it with shifts and masks.
#609 Fix incorrect VCD.
Bump dependent package versions.
Update copyright notice (date).
Add ScalaStyle changes.
Include class hierarchy diagrams in scaladoc
Add support for non-JUint tests.
Removed new line in tester to avoid lots of blank lines for multiple steps.
Fixeds are signed nodes too.
Treat chisel3 compatibility warnings as errors.
Add Chisel3 asUInt()/asSInt().
Flo and Dbl widths are really fixed (and known).
Add support for Chisel3-style "testers as hardware".
Small documentation fixes and comments/questions
Be more selective when re-running to enable line numbers.
Fix broken subword support.

ReleaseNotes for Chisel v2.2.31 2015-12-03

This release of Chisel is largely a maintenance release. See the associated Changelog for issues resolved with this release.

We will be removing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.31 2015-12-03

#603 When validateGen() fails in Reg, mention the failing element.
#595 Improve Tester stability.
#583 Check for empty _log on tester application exit.
#581 Avoid Tester hang on bogus peek()/poke().
#580 Ensure tester mapped memory is marked volatile.
#573 Flo is not printed with printf.
#569 Combinational loop detector is broken.
#556 Module debug for aggregates.
#535 Add more checkpoints in an attempt to report errors sooner.
#534 Add optional message to (most of) expect(Bits, ...).
#531 `Wire(new Bundle { ... })` does not compile.
Bumped Scala build versions to 2.10.6 and 2.11.7
Fix comment in QueueIO.
Fix bad verilog translation of mem and assert (Verilog backend).
No longer use deprecated -use_vpiobj for vcs compilation (Verilog backend).
Add cloneType methods for ArbiterIO and QueueIO Bundles.
Fix Queue object example and add Pipe object example.
Draw Muxes as diamonds with fixed port connections (Dot backend).
OnceOnlyFiles are also unoptimizedFiles (compile -O0) (C++ backend).
Set names for anonymous mems.
Implement rsha_n correctly (C++ backend).
Add optional needsHold parameter to Arbiters.
Fix vcd dump issues in verilog (Verilog backend).
Reintroduce MuxCase / PriorityMux'ing of bundles.

ReleaseNotes for Chisel v2.2.30 2015-10-22

In addition to several bug fixes, this release of Chisel contains a significant change to tester communications. See the associated Changelog for issues resolved with this release.

We will be reducing support for Scala 2.10 in future Chisel releases. Please verify your code compiles and runs correctly under Scala 2.11.

ChangeLog for Chisel v2.2.30 2015-10-22

#563 Update combinational loop analysis.
#559 Deal with exceptions in the test application.
#530 Avoid java.lang.StackOverflowError trying to get widthW().
#528 Generate ChiselError for asserts().
#395 - Deprecate '!=' in favour of '=/='.
Ensure testKeywordsNull() has an application to execute. (Testing)
Update Mem write interface. (Chisel3 compatibility)
Fix spurious Chisel3 Vec compatibility warning. (Chisel3 compatibility)
Fix printf output collection to pass FlushPrintfOutput test. (Testing)
Major overhaul of Tester implementation - use memory mapped files for tester communication. (Testing performance)

ReleaseNotes for Chisel v2.2.29 2015-09-30

In addition to many bug fixes, this release of Chisel adds tester support for gate-level simulation, to facilitate energy modeling and fault injection.

See the associated Changelog for issues resolved with this release.

ChangeLog for Chisel v2.2.29 2015-09-30

#545 Avoid java.lang.UnsupportedOperationException: empty.init when no uncommented ports
#471 An explicit clock for a node should override the explicit reset for a component.
#459 Don't reserve empty names. Slight change to pr499 - ignore attempts to reserve empty names.
Fix error message; remove unused code (that triggers deprecation warning).
Fix a bug in obj id construction
Pass vcd & vpd filenames as arguments
Allow comparison of Node with null.
Fix vpi_put_value timing
Change nameable to Nameable, move setName to Nameable, scope changes
Fix typo (spelling).
Comments and slight modifications to ChiselUtil
Replace gen: T with gen: => T in Vec and Mem constructors and factories. This seems more general and removes the need for a cloneType method on Bundles. Update internal Vec/Mem usage to eliminate deprecation warnings (incomplete - Mem() -> SeqMem() doesn't work since SeqMem() doesn't support an apply() method).
Make sure bfs & dfs visit each node only once
Backend is not abstract now, so NullBackend is not needed
Consistent naming for keywords
Support force to put values on nets in verilog sim
Incorporate Chris's Queue flow and pipe definitions.
Move static class definitions into a class object to placate Scala compiler.
addNode: api for module resolution in custom transforms
Correct error in Queue documentation
Provide a template to reuse tester transactions
Swapped arguments (out,n) in Vec and Mem.
Queue example was not for the object but for class Queue
Make poke(id, v), peek(id) private
Mask the value in dat_from_hex to get the correct value
Disallow Chisel2-style masked writes for SeqMem
Pass reference for put_value
Fix vcd recording for mem
Fix poke bug for long data
Allow for SeqMems to be named via reflection
Remove hasMem flag
Add Chisel3-compatible SeqMem masked writes
Error checking for shift register, negitive number resulted in stack overflow
Fixed vcdMem regression introduced in v28.
Replace overridden setName in seqMem with a working setMemName method
Change nameable to Nameable, move setName to Nameable, scope changes

ReleaseNotes for Chisel v2.2.28 2015-09-02

This release of Chisel adds support for Chisel3 requirements. All currently valid Chisel code should compile unchanged.

Two new options have been added

--minimumCompatibility will issue warnings for usage that is incompatible with the specified version. To issue warnings for currently valid code that will be incompatible with Chisel3, add the following option to your Chisel compilation command:

    --minimumCompatibility 3.0.0

This will report warnings for the following Chisel3 issues -

In order to improve the association of line numbers with warnings, you should also enable the --lineNumbers option.

--wError will turn all compiler warnings into errors. This in combination with the --minimumCompatibility option will help determine if your code is ready for Chisel3.

Look at the Chisel tests for examples of these changes.

See the ChangeLog for additional changes and bug fixes.

ChangeLog for Chisel v2.2.28 2015-09-02

#516 Add missing "d<" operator and Dbl() comparison tests.
#513 Check for unassigned MUX default (conditional assignment) and issue a chisel-specific message "NO DEFAULT SPECIFIED FOR WIRE" instead of: "java.lang.IllegalArgumentException: Flat hash tables cannot contain null elements."
#478 Added a setName method to Module.
#446 Chisel Tutorial uses UFix instead of UInt.
#442 (part b) Add the ability to change timescale in vcd dump file.
#442 (part 1) Correct use of "is" in tutorial FSM switch.
#440 Repeated printfs - clear printStream after returning accumulated output.
#439 Chisel somehow finds a way to build negative width wires.
#438 Add --assertWarn flag converting Assert to Warn.
#431 Use the standard Chisel error mechanism in SystemC backend.
#172 Add a test for issue 172 - unused top level IOs were trimmed.
(Cpp backend) Constant pool literals should be identified by width as well as value.
Update Enum Doc for size > 22 Tuple Limitation and add a test for Enums with more than 22 elements.
Convert project/build.scala to build.sbt
Update scalastyle plugin version.
Make 2.11.6 the default build (and make 2.10.5 the cross scala version).
Fixed comparison between signed and unsigned integer.
Add python-jinja2 to ubuntu documentation dependencies.
Added dependencies for docs build on Mac.
Updated fixed test to randomly test against negatives.
Replace generic "throw new Exception" with Chisel-specific throwException().
Added a setModuleName method to Module.
Added a new BlackBox interface.
Added a DelayBetween method to ChiselUtil to get delays between two nodes.
(Cpp backend) improved multi-word literal support.
Deprecated SFix in favour of Fixed.
Add LargeNumber tests.
Added scaladoc comments.
Always set testerSeed and use it, so printed value is meaningful.
Issue more informative error messages for bad io definitions.
Replace emulator with new emulator api, new testbench & vpi routines.
Clone a copy of the input pin in addPin().
Add Float/Double support to tester.
Chisel3 support - merge chisel3prep branch into master.
Support aggregate types in top level IOs in SystemC backend.
Add Num trait to Complex, introduce conjugate.
Change AsyncQueue references to AsyncFifo.
Add fixed point data type that extends Bits with Num[Fixed]
Add --assertWarn flag converting Assert to Warn.
Stop suppressing compiler warnings for emulator library.
Add parameters manual to the docs.
Cosmetic changes to cheatsheet, installation, and man page.
Removed old maven code.

ReleaseNotes for Chisel v2.2.27 2015-05-19

This release of Chisel:

See the associated Changelog for additional issues resolved with this release.

ChangeLog for Chisel v2.2.27 2015-05-19

#424 Ensure all driver variables are initialized in initChisel().
#410 Correct signature for mem_t::put().
#407 Flag the use of "?" in anything other than comparisons as unsupported.
#406 Literal "+" and "-" shouldn't widen.
#401 Change wire_poke VPI routine to enable POKE on wires and ports wider than 32 bits under VCS simulation.
Reduce resources consumed during graph construction and C++ generation.
Ensure we generate multiple cpp files (when instructed to do so).
Fix bug in VendingMachine Enum example.
Update Complex type (inherit Num trait, introduce conjugate).
Fix null pointer exception for nodes with no component.
Add a hook to calcElements in Bundle to let subclasses of Bundle filter out unwanted member, do type checking, etc.
Fix priority encoder for C++ for >64 bits
Add Wire() no-op (support for Chisel3) and associated tests.
Add MInt() for masked bit comparisons (support for Chisel3); add MInt() test.

ReleaseNotes for Chisel v2.2.26 2015-04-21

This release of Chisel adds support for "test only" operation, to support environments where the construction of the test simulator is decoupled from test execution.

To this end, the following new options have been added:

Using the tutorial "Hello" project as an example, build the test simulator:

 $ sbt  "run hello --genHarness --compile --backend c --vcd"
 [info] Loading global plugins from ...
 [info] ...
 [info] Compiling 1 Scala source to .../chisel-tutorial/hello/target/scala-2.10/classes...
 [info] Running hello.Hello hello --genHarness --compile --backend c --vcd
 CPP elaborate
 [info] [0.048] // COMPILING < (class hello.Hello) > (0)
 [info] [0.058] giving names
 [info] [0.073] executing custom transforms
 [info] [0.074] adding clocks and resets
 [info] [0.087] inferring widths
 [info] [0.098] checking widths
 [info] [0.099] lowering complex nodes to primitives
 [info] [0.099] removing type nodes
 [info] [0.103] compiling 2 nodes
 [info] [0.103] computing memory ports
 [info] [0.103] resolving nodes to the components
 [info] [0.121] creating clock domains
 [info] [0.122] pruning unconnected IOs
 [info] [0.127] checking for combinational loops
 [info] [0.129] NO COMBINATIONAL LOOP FOUND
 [info] [0.152] populating clock domains
 CppBackend::elaborate: need 0, redundant 0 shadow registers
 [info] [0.164] generating cpp files
 CppBackend: createCppFile Hello-0.cpp
 CppBackend: createCppFile Hello-1.cpp
 CppBackend: createCppFile Hello-2.cpp
 CppBackend: createCppFile Hello-3.cpp
 CppBackend: createCppFile Hello-4.cpp
 CppBackend: createCppFile Hello-5.cpp
 CppBackend: createCppFile Hello.cpp
 [info] [0.986] g++ -c -o ./Hello-emulator.o  -I../ -Inull/csrc/  ./Hello-emulator.cpp RET 0
 [info] [1.514] g++ -c -o ./Hello.o  -I../ -Inull/csrc/  ./Hello.cpp RET 0
 [info] [1.573] g++  -o ./Hello ./Hello.o ./Hello-emulator.o RET 0
 [success] Total time: 4 s, completed Apr 17, 2015 8:27:09 AM

run the tests:

 $ sbt  "run hello --test --backend null --vcd --testCommand ./Hello"
 [info] Loading global plugins from ...
 [info] Loading project definition from .../chisel-tutorial/hello/project
 [info] Set current project to chisel-tutorial (in build file:.../chisel-tutorial/hello/)
 [info] Running hello.Hello hello --test --backend null --vcd --testCommand ./Hello
 [info] [0.025] // COMPILING < (class hello.Hello) > (0)
 [info] [0.031] giving names
 [info] [0.042] executing custom transforms
 [info] [0.042] adding clocks and resets
 [info] [0.052] inferring widths
 [info] [0.060] checking widths
 [info] [0.061] lowering complex nodes to primitives
 [info] [0.061] removing type nodes
 [info] [0.063] compiling 2 nodes
 [info] [0.063] computing memory ports
 [info] [0.063] resolving nodes to the components
 [info] [0.077] creating clock domains
 [info] [0.077] pruning unconnected IOs
 [info] [0.080] checking for combinational loops
 [info] [0.082] NO COMBINATIONAL LOOP FOUND
 SEED 1429284499250
 STARTING ./Hello
 RESET 5
 STEP 1 - >  1
 PEEK Hello.io_out - >  0x2a
 EXPECT Hello.io_out  < - 42 == 42 PASS
 RAN 1 CYCLES PASSED
 PASSED
 [success] Total time: 0 s, completed Apr 17, 2015 8:28:19 AM

See the associated Changelog for additional issues resolved with this release.

ChangeLog for Chisel v2.2.26 2015-04-21

#393 Ensure we fail if errors are detected.
#384 Re-work 398c10c fix. This fixes the old issue with SInt ROM generation while still retaining working behavior in deployment (ie. on reference-chip).
#315 Fixes for --allocateOnlyNeededShadowRegisters (don't clobber unshadowed register and keep code order correct).
Support for test only mode.
Add fromMap Method for Bundles (experimental)
Update instructions and commands for generating documentation.
Fix various bugs with addBindings
Chisel error line number reporting - anything above Chisel.chiselMain is user code.

ReleaseNotes for Chisel v2.2.25 2015-03-25

This release of Chisel is largely a maintenance release. See the associated Changelog for issues resolved with this release.

ChangeLog for Chisel v2.2.25 2015-03-25

Detect and issue an error for double Module() wrapping - #385
Fix Data width lost in Vec #384.
For test, use JUnitSuite over AssertionsForJUnit
In Verilog, fix bug for similar modules, some not emitted
Better Namespace conflict resolution for Verilog
Fix for multiply instantiated modules in Chisel result in redundant (functionally equivalent) module definitions in generated Verilog #374
In CPP, better detection of signals to randomize
Disallow comparisons between Nodes and non-Nodes
Include type of missing Parameter in error message
Address issue with width-inference of right-shift
Update emulator_{api,mod}.h to eliminate C++ compiler warnings.
Update README to reflect current build procedure.

ReleaseNotes for Chisel v2.2.24 2015-03-09

This release of Chisel is largely a maintenance release. See the associated Changelog for issues resolved with this release.

This release provides initial support for Scala 2.11. In order to use the 2.11 version of the code, change the scalaVersion definition in your build.sbt (or build.scala) file from:

scalaVersion := "2.10.x"

to:

scalaVersion := "2.11.4"

NOTE: Expect three warnings when compiling under Scala 2.11:

[warn] src/main/scala/Parameters.scala:272: abstract type T in type pattern Chisel.Ex[T] is unchecked since it is eliminated by erasure
[warn]           case ex:Ex[T] = >  _bindLet[T](pname,ex)
[warn]                   ^
[warn] src/main/scala/Parameters.scala:271: abstract type T in type pattern Chisel.Knob[T] is unchecked since it is eliminated by erasure
[warn]           case k:Knob[T] = >  ExVar[T](_VarKnob[T](k.name))
[warn]                  ^
[warn] src/main/scala/Parameters.scala:272: abstract type T in type pattern Chisel.Ex[T] is unchecked since it is eliminated by erasure
[warn]           case ex:Ex[T] = >  _bindLet[T](pname,ex)
[warn]                   ^
model contains 286 documentable templates
[warn] three warnings found

ChangeLog for Chisel v2.2.24 2015-03-09

Convert from unsupported sbt-scct to scoverage.
Fix bug in applying new parameters via bundle factory
Initial support for Scala 2.11

ReleaseNotes for Chisel v2.2.22 2015-02-26

This release of Chisel is largely a maintenance release. See the associated Changelog for issues resolved with this release.

Muxes of type Bits now use SInt (previously, UInt) This fixes issue #358 and constitutes behavioral change. To facilitate any necessary porting, a warning is now issued when a Mux of type Bits is created. This warning will likely be turned off or removed in future versions. Justification behind using SInt over UInt is so that corresponding sign extension is better aligned to C semantics.

ChangeLog for Chisel v2.2.22 2015-02-26

#363 Convert to C++ getline() semantics
#363 Break out of read_eval_print_loop() if getline() returns an error.
#363 Check File pointers are non-NULL before trying to fclose() them.
#359 Weird compiler error for write-masked Mems in Verilog backend.
#358 Muxes of type Bits now use SInt (previously, UInt).
#356 : Tester.expect always results a PASS on data wider than 32 bits, even when signal value does not much the expected value.
#265 Wrong verilog generated from When X{ when Y{ reg := }} otherwise { reg := }.
#191 Randomize unconnected Verilog wires (as we do for the C++ backend).
Fix fromNode involving zero-width wires.
Fixes from HPCA workshop.
Minor fixes to the tutorial.
Use signal names from parent objects (implicit reset may have a different name).
Support Quartus' variant of `ifndef SYNTHESIS.
Work around bug causing illegal assignment of static const variable.
Don't accept negative UInt literals.

ReleaseNotes for Chisel v2.2.21 2014-12-12

This release of Chisel is largely a maintenance release. See the associated Changelog for issues resolved with this release.

ChangeLog for Chisel v2.2.21 2014-12-12

#347 Mishandling of UInts with MSB == 1
#346 Signals only used as resets are trimmed
#335 Null Pointer Exception on Floating Output.
#334 Fix poking Negative Values Fails
#325 ChiselUtil Reverse: Cpp optimization floods console with warnings
Eliminate NullPointerException if computeMemPorts is called before forceMatchingWidth.
Reorder Chisel standard passes for performance and flexibility.
Simplify and speed up width inference.
Placate various C++ compilers (C++ backend).
Minor changes to the dot backend for literal node names in debugging support (Dot backend).
Fixes to binding and register naming.

ReleaseNotes for Chisel v2.2.20 2014-11-20

This release of Chisel is largely a maintenance release. See the associated Changelog for issues resolved with this release.

There were significant changes to the Bundle and Vec code:

  1. Make the flatten methods generate correct element names
  2. Internal data structures
    • Bundle: LinkedHashMap(name & io pairs)
    • Vec: Vector(now Vec is immutable)
  3. Remove legacy code

There were significant changes to Verilog testing:

  1. Use vpi routines for verilog tests
  2. Fix timing and compile errors of verilog tests
  3. Generate the same harness regardless of the --test option

ChangeLog for Chisel v2.2.20 2014-11-20

#94 printf being discarded during elaboration
#153 nameIt is way too eager, needs to chill out
#168 lit as port breaks chisel - flag it as a ChiselError
#196 README Instructions don't let to a working HelloWorld
#209 enerated Verilog repeated wire names (Verilog backend)
#286 Width Inference Issue (width of operations on literals)
#290 Register with custom clock for a bundle generate wrong verilog
#292 Vcd varName,stripComponent code emits invalid variable IDs
#295 Bundle.calcElements calculates too many
#298 Printf() doesn't since the switch to the new Tester
#300 Generated cpp files lack Config substring (C++ backend)
#319 --parallelMakeJobs doesn't understand --targetDir
#321 Support poking large numbers - extension of #318
#331 Fill(0, ...) fails with a java exception
Vtests: fix step
Deleted unused ModularCpp backend before more bitrot sets in.
Cosmetic/scalastyle fixes - no functional changes.
Add support for a constant pool (C++ backend)
Add hasSRAM & sramMaxSize for custom transforms
Fix naming problems when adding modules in custom transforms
Parametrization in custom transforms
Fix a binding problem
Fixes to --partitionIslands
Small changes in parameterization
Added "in" operator that can be used when defining constraints. Currently only works for List[Int], Range, and List[Chisel.IntEx]
Significant rewrite of the Bundle and Vec code
Significant changes to Verilog test code

ReleaseNotes for Chisel v2.2.19 2014-10-03

This release of Chisel adds support for:

We are introducing experimental support to Chisel to allow module designers to specify design parameters that should be configured on the fly as the design is elaborated. We provide support for looking up parameter values within Chisel Modules and Bundles, as well as scoping where certain parameter values are defined and customizing how dependent parameters are calculated. Users can define custom ChiselConfiguration classes which override default parameter values, and they can select which configuration to use at runtime via the Chisel command line. We allow constraints to be placed on parameter values and provide hooks for automated design space exploration of parameter spaces. A detailed guide to these experimental features is available at in the Chisel repo at chisel/doc/parameters/parameters.pdf

0-width wire support attempts to eliminate 0-width wires from the design by either replacing them with the appropriate identity element, or by removing them entirely. This feature is highly experimental and is controlled by the --W0W command line option to Chisel.

The C++ backend changes attempt to improve compilation performance by reducing the size of the functions generated by the C++ backend. This feature is highly experimental and is controlled by a number of Chisel command line options. The following options are either treated as simple binary feature enablers, or take an < Integer > argument specifying the value of some optional feature.

--allocateOnlyNeededShadowRegisters (C++ backend) Attempt to allocate only those shadow registers actually required. This reduces the size of the main C++ design object (especially when --shadowRegisterInObject is enabled), which in turn reduces compilation time. It should have no execution-time performance impact.
--compileInitializationUnoptimized (C++ backend) Compile initialization code at -O0, rarely used code at -O1.
--isVCDinline (C++ backend) Generate VCD dump code without goto branches. Allows compiling smaller VCD dump functions, reducing C++ compile times. This will have some impact on execution-time performance.
--lineLimitFunctions < Integer > (C++ backend) Limit the number of lines in a C++ function/method before splitting it up into multiple functions to reduce C++ compile times. The < Integer > value specifies a loose upper limit on the number of lines output to a single function before that function is split up into smaller functions. This involves a trade-off between compile-time performance and execution-time performance. Smaller functions yield faster compile times, but result in slower execution since instead of calling a single function, calls to multiple functions are generated. Reasonable values for this argument would be in the range from 256 to 2048.
--minimumLinesPerFile < Integer > (C++ backend) Limit the minimum number of lines per file so as not to produce trivial files. This works in conjunction with --lineLimitFunctions to break up a massive single file into multiple smaller (but not too small) files. Reasonable values for this argument would be in the range of 1024 to 32768.
--parallelMakeJobs < Integer > (C++ backend) Generate a Makefile to compile multiple C++ files in parallel. The < Integer > argument specifies the amount of parallelism (the argument to the -j option to make). A value of -1 indicates that no value will be passed with the -j argument to make, which in turn should inform make not to limit the number of jobs that can run simultaneously.
--partitionIslands (C++, dot backends) Partition the graph into islands of combinatorial logic that may be compiled and executed in parallel.
--shadowRegisterInObject (C++ backend) Allocate shadow registers in the global emulation object (as opposed to the local clock procedures). This is automatically enabled when --lineLimitFunctions is in effect.

ChangeLog for Chisel v2.2.19 2014-10-03

#76 Width inference takes hours, needs to quickly detect and throw error on un-inferable code
#83 log2Up(1) returns 1, instead of the correct answer of 0
#86 Queue is generating incorrect code; io.deq signals don't match io.enq signals.
#124 zero width wire support
#176 Re-enable testEqlBundle() and testEqlVec() after inserting explicit toBits comversion.
#209 Queue is generating incorrect code; io.deq signals don't match io.enq signals.
#247 Vec getWidth return zero
#248 ,249 Update ShiftRegister to support a parameterized delay of 0.
#251 make assertions an option in driver
#257 initialize register that guards reset for assert checking
#259 C++ compilation speedups
#263 No Explicit Error When Writing To Your Inputs
Support poking negative numbers.
Add "tolerant" Float expect - accept single bit differences between expected and returned values.
Changed default behavior for Parameter.empty to throw ParameterUndefinedException and KnobUndefinedException