Constructing Hardware in a Scala Embedded Language

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Save the Date: Chisel Community Conference Tuesday 11/13-14

We are holding the first Chisel Community Conference, located in the Bay Area, on November 13-14, 2018 (more details forthcoming). This will be the first event promoting the Chisel language, FIRRTL compiler, and associated software ecosystem, bringing together the community for multiple talks, tutorials, exhibitions and more.


We are accepting contributions for presentation at the conference. Submissions will be for a 10-20 minute talk and/or poster, and should consist of a <750 word abstract and optional additional material. Topics include extensions to the Chisel frontend or FIRRTL compiler, Chisel libraries, Chisel-based projects (such as Rocketchip-based designs), Chisel-related infrastructure (testers, transforms, backends, simulators), Chisel in teaching, and other tools/contributions that promote reusability in hardware. The closing date for submissions is Friday, September 14.


IMPORTANT: Please sign up for the new chisel-announce group for all future details regarding CCC, as well as other Chisel announcements!

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using metaprogramming in Scala
  • Supports layering of domain specific languages
  • Sizeable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on github with modified BSD license
  • Complete set of docs
  • Growing community of adopters

You can find code examples on the Berkeley EECS Berkeley Architecture Research (BAR) github page. Chisel-tutorial is a set of sample circuits with supporting Sodor is a set of educational processors written in Chisel by Christopher Celio, a PhD student at UC Berkeley. Sodor implements the RISC-V Instruction Set Architecture designed in the BAR group and described on

import chisel3._

class GCD extends Module {
  val io = IO(new Bundle {
    val a  = Input(UInt(32.W))
    val b  = Input(UInt(32.W))
    val e  = Input(Bool())
    val z  = Output(UInt(32.W))
    val v  = Output(Bool())
  val x = Reg(UInt(32.W))
  val y = Reg(UInt(32.W))
  when (x > y)   { x := x -% y }
  .otherwise     { y := y -% x }
  when (io.e) { x := io.a; y := io.b }
  io.z := x
  io.v := y === 0.U
import chisel3._

class MaxN(val n: Int, val w: Int) extends Module {

  private def Max2(x: UInt, y: UInt) = Mux(x > y, x, y)

  val io = IO(new Bundle {
    val ins = Input(Vec(n, UInt(w.W)))
    val out = Output(UInt(w.W))
  io.out := io.ins.reduceLeft(Max2)

import chisel3._
import scala.collection.mutable.ArrayBuffer

/** Four-by-four multiply using a look-up table.
class Mul extends Module {
  val io = IO(new Bundle {
    val x   = Input(UInt(4.W))
    val y   = Input(UInt(4.W))
    val z   = Output(UInt(8.W))
  val muls = new ArrayBuffer[UInt]()

  // -------------------------------- \\
  // Calculate io.z = io.x * io.y by
  // building filling out muls
  // -------------------------------- \\

  for (i <- 0 until 16)
    for (j <- 0 until 16)
      muls += (i * j).U(8.W)
  val tbl = Vec(muls)
  io.z := tbl((io.x << 4.U) | io.y)

import chisel3._
import chisel3.util._

//A n-bit adder with carry in and carry out
class Adder(val n:Int) extends Module {
  val io = IO(new Bundle {
    val A    = Input(UInt(n.W))
    val B    = Input(UInt(n.W))
    val Cin  = Input(UInt(1.W))
    val Sum  = Output(UInt(n.W))
    val Cout = Output(UInt(1.W))
  //create an array of FullAdders
  val FAs   = Array.fill(n)(Module(new FullAdder()).io)
  val carry = Wire(Vec(n+1, UInt(1.W)))
  val sum   = Wire(Vec(n, Bool()))

  //first carry is the top level carry in
  carry(0) := io.Cin

  //wire up the ports of the full adders
  for (i <- 0 until n) {
    FAs(i).a := io.A(i)
    FAs(i).b := io.B(i)
    FAs(i).cin := carry(i)
    carry(i+1) := FAs(i).cout
    sum(i) := FAs(i).sum.toBool()
  io.Sum := Cat(sum.reverse)
  io.Cout := carry(n)

Getting started with Chisel is easy. Its DSL is built on familiar concepts. Boilerplate verilog often directly maps to Chisel one-liners. Integration with the Scala language simplifies the expression of complicated circuits.

Chisel is released as a collection of JARs file published through the official Maven repo. Check out the Generator Bootcamp for a self-paced interactive tutorial in a Jupyter notebook and be running Chisel right away.

Chisel uses the Scala Language

riscv-sodor Educational microarchitectures for risc-v isa (Christopher Celio)
Patmos Time-predictable VLIW processor (T-CREST)
chisel-examples Chisel Blink, Counter and FSM Examples (Martin Schoeberl)
OpenSoC Fabric A Parameterizable NoC (LBL Computer Architecture Lab)
RoCC Neural Network Accelerator Neural network software/hardware for RISC-V microprocessors Boston University

To Add your project to the list, just advertise about it on the Chisel mailing list!