Packages

object Mux4Cell

Utility for constructing 4-to-1 MUX cell intrinsic. This intrinsic is lowered into verilog with vendor specic pragmas that guarantee utilization of 4-to-1 MUX cell in the synthesis process.

Source
Synthesis.scala
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  1. final def !=(arg0: Any): Boolean
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  4. def apply[T <: Data](sel: UInt, v3: T, v2: T, v1: T, v0: T): T

    Creates an intrinsic which will be lowered to a 4-to-1 MUX cell in synthesis tools.

    Creates an intrinsic which will be lowered to a 4-to-1 MUX cell in synthesis tools.

    sel

    2-bit unsigned integer determining the input to choose.

    v3

    the value chosen when selector is 3

    v2

    the value chosen when selector is 2

    v1

    the value chosen when selector is 1

    v0

    the value chosen when selector is 0

    Example:

    1. v := Mux4Cell(sel, v3, v2, v1, v0)
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